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datasheet ics854s01aki june 15, 2017 1 ?2017 integrated device technology, inc. 2:1 differential-to-lvds multiplexer ICS854S01I general description the ICS854S01I is a high performance 2:1 differential-to-lvds multiplexer. the ICS854S01I can also perform differential translation because the differential inputs accept lvpecl, lvds or cml levels. the ICS854S01I is packaged in a small 3mm x 3mm 16 vfqfn package, making it ideal for use on space constrained boards. features ? 2:1 lvds mux ? one lvds output pair ? two differential clock inputs can accept: lvpecl, lvds, cml ? maximum input/output frequency: 2.5ghz ? translates lvcmos/lvttl input signals to lvds levels by using a resistor bias network on npclk0, npclk1 ? rms additive phase jitter: 0.06ps (typical) ? propagation delay: 600ps (maximum) ? part-to-part skew: 350ps (maximum) ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 pclk0 n pclk0 pclk1 n pclk1 gn d q nq gn d r eserved clk_sel nc v dd gn d gn d v dd nc 0 1 q n q pclk0 npclk0 pclk1 c lk_sel npclk1 pulldown pullup/pulldown pulldown pulldown pullup/pulldown ICS854S01I 16-lead vfqfn 3mm x 3mm x 0.925mm package body k package top view block diagram pin assignment
ics854s01aki june 15, 2017 2 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3. control input function table number name type description 1 pclk0 input pulldown non-inverting differential clock input. 2 npclk0 input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 3 pclk1 input pulldown non-inverting differential clock input. 4 npclk1 input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 5 reserved reserve reserve pin. 6 clk_sel input pulldown clock select input. when high, selects pclk1, npclk1 inputs. when low, selects pclk0, npclk0 inputs. lvcmos / lvttl interface levels. 7, 16 nc unused no connects. 8, 13 v dd power power supply pins. 9, 12, 14, 15 gnd power power supply ground. 10, 11 nq, q output differential output pair. lvds interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 2 pf r pullup input pullup resistor 37 k ? r pulldown input pulldown resistor 37 k ? clk_sel pclk selected 0 pclk0, npclk0 1 pclk1, npclk1
ics854s01aki june 15, 2017 3 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4c. lvpecl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ? ja 74.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v i dd power supply current 40 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk_sel v dd = v in = 3.465v 150 a i il input low current clk_sel v dd = 3.465v, v in = 0v -10 a symbol parameter test conditions minimum typical maximum units i ih input high current pclk0, npclk0, pclk1, npclk1 v dd = v in = 3.465v 150 a i il input low current pclk0, pclk1 v dd = 3.465v, v in = 0v -10 a npclk0, npclk1 v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.2 v v cmr common mode input voltage; note 1, 2 1.2 v dd v
ics854s01aki june 15, 2017 4 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer table 4d. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note: all parameters measured at ? 1.0ghz unless otherwise noted. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: q, nq outputs measured differentially. see parameter measurement information to mux isolation diagram. symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditions minimum typical maximum units f out output frequency 2.5 ghz t pd propagation delay; note 1 250 400 600 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz) 0.06 ps t sk(pp) part-to-part skew; note 2, 3 350 ps t r / t f output rise/fall time 20% to 80% 100 275 ps odc output duty cycle 49 51 % mux_ isolation mux isolation; note 4 f out = 155.52mhz, v pp = 400mv 86 db
ics854s01aki june 15, 2017 5 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator ?ifr2042 10khz ? 56.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator? additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.06ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ics854s01aki june 15, 2017 6 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer parameter measurement information lvds output load ac test circuit part-to-part skew output rise/fall time differential input level mux isolation propagation delay scope q nq 3.3v5% power supply +? float gnd v dd nqx qx nqy qy t sk(pp) p art 1 p art 2 20% 80% 80% 20% t r t f v od q nq npclk[0:1] pclk[0:1] v dd gnd v cmr cross points v pp amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static inp ut mux selects active input clock signal a1 t pd nq q npclk[0:1] pclk[0:1
ics854s01aki june 15, 2017 7 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer parameter measurement information, continued output duty cycle/pulse width/period offset voltage setup differential output voltage setup q nq
ics854s01aki june 15, 2017 8 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer application information wiring the differential input to accept single ended levels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ended signal driving differential input recommendations for unused input pins inputs: pclk/npclk inputs: for applications not requiring the use of the differential input, both pclk and npclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. r2 1k v dd clk_in r1 1k c1 0.1uf v_ref pclkx npclkx
ics854s01aki june 15, 2017 9 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2c show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a 3.3v lvds driver figure 2c. pclk/npclk input driven by a 3.3v lvpecl driver figure 2e. pclk/npclk input driven by a cml driver figure 2b. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple figure 2d. pclk/npclk input driven by a built-in pullup cml driver r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 pclk npclk 3.3v 3.3v lvpecl lvpec l input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 pclk npclk 3.3v 3.3v lvpecl lvpec l input pclk npclk lvpecl input cml 3.3v zo = 50 zo = 50 3.3v 3.3v r1 50 r2 50 pclk npclk 3.3v lvpec l input 3.3v zo = 50 zo = 50 r1 100 cml built-in pullup
ics854s01aki june 15, 2017 10 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer application schematic example figure 3 shows an example of ICS854S01I application schematic. this device can accept different types of input signal. in this example, the input is driven by a lvds driver. the decoupling capacitor should be located as close as possible to the power pin. note: thermal pad (e-pad) must be connected to ground (gnd). figure 3. ICS854S01I application schematic example
ics854s01aki june 15, 2017 11 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics854s01aki june 15, 2017 12 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer 3.3v lvds driver termination a general lvds interface is shown in figure 5 in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 5. typical lvds driver termination 3.3v lvds driver r1 100 ? + 3.3v 50 50 100 differential transmission line
ics854s01aki june 15, 2017 13 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer power considerations this section provides information on power dissipation and junction temperature for the ICS854S01I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for theICS854S01I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 40ma = 138.6mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.139w * 74.7c/w = 95.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16 lead vfqfn, forced convection ? ja by velocity meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics854s01aki june 15, 2017 14 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer reliability information table 7. ? ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ICS854S01I is: 257 this is a suggested replacement for ics85401 ? ja by velocity meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics854s01aki june 15, 2017 15 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer package drawings ? sheet 1
ics854s01aki june 15, 2017 16 ?2017 integrated device technology, inc. ICS854S01I datasheet 2:1 differential-to-lvds multiplexer package drawings ? sheet 2
ICS854S01I datasheet 2:1 differential-to-lvds multiplexer disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at idt?s sole discretion. performance specifications and operating parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual p roperty rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com ordering information table 9. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. revision history part/order number marking package shipping packaging temperature 854s01akilf 4s1a ?lead-free? 16 lead vfqfn tube -40 ? c to 85 ? c 854s01akilft 4s1a ?lead-free? 16 lead vfqfn tape & reel -40 ? c to 85 ? c date description of change 6/15/2017 updated the package drawings 11/2/2012 added note: thermal pad (e-pad) must be connected to ground (gnd). 10/29/2012 deleted hiperclocks logo. updated gd paragraph to include cml. added cml to 3rd bullet. added figures 2d and 2e. deleted quantity from tape and reel.

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